Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 273
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
CLOCK_DEDICATED_ROUTE Constraints
System Clock
If the SRCC/MRCC I/O pin and PLL are not allocated in the same bank, the
CLOCK_DEDICATED_ROUTE constraint must be set to BACKBONE. DDR3/DDR2 SDRAM
manages these constraints for designs generated with the System Clock option selected as
Differential/Single-Ended (at FPGA Options > System Clock).
If the design is generated with the System Clock option selected as No Buffer (at FPGA
Options > System Clock), the CLOCK_DEDICATED_ROUTE constraints based on the
SRCC/MRCC I/O and PLL allocation needs to be handled manually for the IP flow.
DDR3/DDR2 SDRAM does not generate clock constraints in the XDC file for the No Buffer
configurations. You must take care of the clock constraints for the No Buffer configurations
in the IP flow.
Reference Clock
If the SRCC/MRCC I/O pin and MMCM are not allocated in the same bank, the
CLOCK_DEDICATED_ROUTE constraint is set to FALSE. Reference clock is a 200 MHz clock
source used to drive IODELAY CTRL logic (through an additional MMCM). This clock is not
utilized, CLOCK_DEDICADE_ROUTE (as they are limited in number), hence the FALSE value is
set. DDR3/DDR2 SDRAM manages these constraints for designs generated with the System
Clock option selected as Differential/Single-Ended (at FPGA Options > System Clock).
If the design is generated with the System Clock option selected as No Buffer (at FPGA
Options > System Clock), the CLOCK_DEDICATED_ROUTE constraints based on
SRCC/MRCC I/O and MMCM allocation needs to be handled manually for the IP flow.
DDR3/DDR2 SDRAM does not generate clock constraints in the XDC file for the No Buffer
configurations. You must take care of the clock constraints for the No Buffer configurations
in the IP flow.
Send Feedback

Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English