Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 472
UG586 November 30, 2016
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Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Do not drive user clocks through the I/O clocking backbone from the region(s) containing
the MIG generated memory interface to CMT blocks in adjacent regions due to resource
limitations. For more information, see the 7 Series FPGAs Clocking Resources User Guide
(UG472) [Ref 10].
The MIG tool sets the VCCAUX_IO constraint based on the data rate and voltage input
selected. The generated XDC has additional constraints as needed. For example:
# PadFunction: IO_L13P_T2_MRCC_37
set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_p}]
set_property IOSTANDARD DIFF_HSTL_I [get_ports {sys_clk_p}]
set_property PACKAGE_PIN K22 [get_ports {sys_clk_p}]
# PadFunction: IO_L13N_T2_MRCC_37
set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_n}]
set_property IOSTANDARD DIFF_HSTL_I [get_ports {sys_clk_n}]
set_property PACKAGE_PIN J22 [get_ports {sys_clk_n}]
For more information, see the Xilinx Timing Constraints Guide (UG612) [Ref 15].
For RLDRAM II interfaces that have the memory system input clock (sys_clk_p/sys_clk_n)
placed on CCIO pins within one of the memory banks, MIG assigns the DIFF_HSTL_I I/O
standard (VCCO = 1.5V) to the CCIO pins. Because the same differential input receiver is
used for both DIFF_HSTL_I and LVDS inputs, an LVDS clock source can be connected directly
to the DIFF_HSTL_I CCIO pins. For more details on usage and required circuitry for LVDS and
LVDS_25 I/O Standards, see the 7 Series FPGAs SelectIO™ Resources User Guide (UG471)
[Ref 2].
Termination
These recommendations apply to termination for RLDRAM II and RLDRAM 3 memory
interface solution:
• Simulation (using IBIS or other) is highly recommended. The loading of command and
address signals depends on various factors, such as speed requirements and
termination topology. Loading can be a limiting factor in reaching a performance
target.
• Command and Address signals should be terminated to V
TT
through a 40Ω resistor if
operating at and above 1,333 Mb/s, or 50Ω if operating below 1,333 Mb/s.
• Data signals (DQ) do not require an external termination, and should use DCI. Set DCI
termination to 40Ω for operation at and above 1,333 Mb/s, or 50Ω if operating below
1,333 Mb/s.
• Data Mask (DM) does not require an external termination, as On-Die Termination (ODT)
is sufficient.
• QVLD (RLDRAM 3 only) does not require an external termination and should use DCI.
Set DCI termination to 40Ω for operation at and above 1,333 Mb/s, or 50Ω if operating
below 1,333 Mb/s.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English