Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 90
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
10. Run implementation flow with the Vivado tool. For details about implementation, see
the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 7].
Note:
Similar steps can be followed for the user design using appropriate .dcp and .xdc files.
Core Architecture
This section describes the architecture of the 7 series FPGAs memory interface solutions
core, providing an overview of the core modules and interfaces.
Overview
The 7 series FPGAs memory interface solutions core is shown in Figure 1-51.
X-Ref Target - Figure 1-51
Figure 1-51: 7 Series FPGAs Memory Interface Solution
rst
clk
app_addr
app_cmd
app_en
app_hi_pri
app_wdf_data
app_wdf_end
app_wdf_mask
app_wdf_wren
app_rdy
app_rd_data
app_rd_data_end
app_rd_data_valid
app_wdf_rdy
app_sr_req
app_sr_active
app_ref_req
app_ref_ack
app_zq_req
app_zq_ack
ddr_ad dr
ddr_ba
ddr_cas_n
ddr_ck
ddr_cke
ddr_cs_n
ddr_dm
ddr_o dt
ddr_ra s_n
ddr_reset_n
ddr we n
ddr_dq
ddr_dqs_n
ddr_dqs
User
FPGA
Logic
DDR2/DDR3
SDRAM
User
Interface
Block
Memory
Controller
Physical
Layer
7 Series FPGAs Memory Interface Solution
User Interface
(1)
Physical Interface
7 Series FPGAs
Native Interface
MC/PHY Interface
ddr_ck_n
ddr_parity
IOB
1. System clock (sys_clk_p and sys_clk_n/sys_clk_i), Reference clock (clk_ref_p and clk_ref_n/clk_ref_i), and system reset (sys_rst_n) port
connections are not shown in block diagram.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English