Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 39
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Setting DDR3 Memory Parameter Option
This feature allows the selection of various memory mode register values, as supported by
the controller specification (Figure 1-21).
The mode register value is loaded into the load mode register during initialization. Only
burst length 8 (BL8) is supported for DDR2 and DDR3 SDRAM.
The Output Driver Impedance Control sets the output driver impedance on the DRAM.
The selections listed are determined by specific DRAM chosen. RZQ is 240Ω. For example,
if RZQ/6 is chosen, the output drive impedance is 40Ω. For more information, consult the
memory vendor data sheet.
The DDR2 SDRAM interface has a separate option to select the number of memory clocks
called Memory Clock Selection. Each component has a Number of Memory Clocks
setting, and the maximum number of clocks allowed is four.
X-Ref Target - Figure 1-21
Figure 1-21: Setting Memory Mode Options
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