Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 497
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Synthesis and Implementation Debug
Figure 3-77 shows the debug flow for synthesis and implementation.
IMPORTANT: The standard synthesis flow for Synplify is not supported for the core.
Verify Successful Synthesis and Implementation
The example design and user design generated by the MIG tool include
synthesis/implementation script files and .xdc files. These files should be used to properly
synthesize and implement the targeted design and generate a working bitstream.
Verify Modifications to the MIG Tool Output
The MIG tool allows you to select the FPGA banks for the memory interface signals. Based
on the banks selected, the MIG tool outputs a XDC with all required location constraints.
This file is located in both the example_design/par and user_design/par directories
and should not be modified.
The MIG tool outputs open source RTL code parameterized by top-level HDL parameters.
These parameters are set by the MIG tool and should not be modified manually. If changes
are required, such as decreasing or increasing the frequency, the MIG tool should be rerun
to create an updated design. Manual modifications are not supported and should be
verified independently in behavioral simulation, synthesis, and implementation.
Identifying and Analyzing Timing Failures
The MIG tool RLDRAM II/RLDRAM 3 designs have been verified to meet timing using the
example design across a wide range of configurations. However, timing violations might
occur, such as when integrating the MIG tool design with your specific application logic.
X-Ref Target - Figure 3-77
Figure 3-77: Synthesis and Implementation Debug Flowchart
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)MPLEMENTATION5SING%XAMPLE$ESIGN
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6ERIFY3UCCESSFUL3YNTHESISAND
)MPLEMENTATION5SING5SER$ESIGN
6ERIFY$ESIGN4IMINGIN42!#%
/PEN7EB#ASE
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