Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 126
UG586 November 30, 2016
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Precharge Policy
The controller implements an aggressive precharge policy. The controller examines the
input queue of requests as each transaction completes. If no requests are in the queue for
a currently open bank/row, the controller closes it to minimize latency for requests to other
rows in the bank. Because the queue depth is equal to the number of bank machines,
greater efficiency can be obtained by increasing the number of bank machines
(nBANK_MACHS). As this number is increased, FPGA logic timing becomes more
challenging. In some situations, the overall system efficiency can be greater with an
increased number of bank machines and a lower memory clock frequency. Simulations
should be performed with the target design command behavior to determine the optimum
setting.
Note:
The overall read latency of the MIG 7 series DDR3/DDR2 core is dependent on how the
Memory Controller is configured, but most critically on the target traffic/access pattern and the
number of commands already in the pipeline before the read command is issued. Read latency is
measured from the point where the read command is accepted by the user or native interface.
Simulation should be run to analyze read latency.
Error Correcting Code
The Memory Controller optionally implements an Error Correcting Code (ECC). This code
protects the contents of the DRAM array from corruption. A Single Error Correct Double
Error Detect (SECDED) code is used. All single errors are detected and corrected. All errors
of two bits are detected. Errors of more than two bits might or might not be detected.
Figure 1-54 shows the ECC block diagram. These blocks are instantiated in the Memory
Controller (mc.v) module.
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