Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 286
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
MIG outputs are generated with the folder name <component name>.
IMPORTANT: Only alphanumeric characters can be used for <component name>. Special characters
cannot be used. This name should always start with an alphabetical character and can end with an
alphanumeric character.
When invoked from Xilinx Platform Studio (XPS), the component name is corrected to be
the IP instance name from XPS.
3. Click Next to display the Pin Compatible FPGAs page.
Pin Compatible FPGAs
The Pin Compatible FPGAs page lists FPGAs in the selected family having the same
package. If the generated pinout from the MIG tool needs to be compatible with any of
these other FPGAs, this option should be used to select the FPGAs with which the pinout
has to be compatible (Figure 2-15).
X-Ref Target - Figure 2-14
Figure 2-14: MIG Output Options
UG586_c1_09_120311
Send Feedback

Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V