Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 587
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Internal (FPGA) Logic Clock
The internal FPGA logic is clocked by a global clocking resource at a half frequency of the
LPDDR2 SDRAM clock frequency. This MMCM also outputs the high-speed LPDDR2
memory clock.
Write Path (Output) I/O Logic Clock
The output path comprising both data and controls is clocked by PHASER_OUT. The
PHASER_OUT provides synchronized clocks for each byte group to the OUT_FIFOs and to
the OSERDES/ODDR. The PHASER_OUT generates a byte clock (OCLK), a divided byte clock
(OCLKDIV), and a delayed byte clock (OCLK_DELAYED) for its associated byte group. These
clocks are generated directly from the Frequency Reference clock and are in phase with
each other. The byte clock is the same frequency as the Frequency Reference clock and the
divided byte clock is half the frequency of the Frequency Reference clock. OCLK_DELAYED is
used to clock the DQS ODDR to achieve the required 90° phase offset between the write
DQS and its associated DQ bits.
The PHASER_OUT also drives the signaling required to generate DQS during writes, the DQS
and DQ 3-state associated with the data byte group, and the Read Enable for the OUT_FIFO
of the byte group. The clocking details of the address/control and the write paths using
PHASER_OUT are shown in Figure 4-50 and Figure 4-52.
Read Path (Input) I/O Logic Clock
The input read datapath is clocked by the PHASER_IN block. The PHASER_IN block provides
synchronized clocks for each byte group to the IN_FIFOs and to the IDDR/ISERDES. The
PHASER_IN block generates two delayed clocks for LPDDR2 SDRAM data captures: read
byte clock (ICLK) and read divided byte clock (ICLKDIV). ICLK is the delayed version of the
frequency reference clock. ICLKDIV is used to capture data into the first rank of flip-flops in
the ISERDES. ICLKDIV is aligned to ICLK and is the parallel transfer clock for the last rank of
flip-flops in the ISERDES. ICLKDIV is also used as the write clock for the IN_FIFO associated
with the byte group. The clocking details of the read path using PHASER_IN is shown in
Figure 4-52.
IDELAY Reference Clock
A 200 MHz IDELAY clock must be supplied to the IDELAYCTRL module. The IDELAYCTRL
module continuously calibrates the IDELAY elements in the I/O region to account for
varying environmental conditions. The IP core assumes an external clock signal is driving
the IDELAYCTRL module. If a PLL clock drives the IDELAYCTRL input clock, the PLL lock
signal needs to be incorporated in the rst_tmp_idelay signal inside the
IODELAY_CTRL.v module. This ensures that the clock is stable before being used.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English