Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 117
UG586 November 30, 2016
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
wr_data_offset
This bus is used to step through the data buffer when the burst length requires more than
a single cycle to complete. This bus, in combination with wr_data_addr, can be applied to
the address input of a buffer in the user design.
Read Command Signals
The native interface provides a set of signals used when the Memory Controller is
processing a read command (Table 1-53). These signals are similar to those for processing
write commands, except that they transfer data from the memory device to a buffer in the
user design.
rd_data
This bus is the data that was read from the external memory. It can be connected to the data
input of a buffer in the user design.
rd_data_addr
This bus is an echo of data_buf_addr when the current read request is submitted. This
bus can be combined with the rd_data_offset signal and applied to the address input of
a buffer in the user design.
rd_data_en
This signal indicates when valid read data is available on rd_data for a read request. It can
be tied to the chip select and write enable of a buffer in the user design.
rd_data_offset
This bus is used to step through the data buffer when the burst length requires more than
a single cycle to complete. This bus can be combined with rd_data_addr and applied to
the address input of a buffer in the user design.
Table 1-53: Native Interface Read Command Signals
Signal Direction Description
rd_data[2 × nCK_PER_CLK × PAYLOAD_WIDTH – 1:0] Output
This is the output data from read
commands.
rd_data_addr[DATA_BUF_ADDR_WIDTH – 1:0] Output
This output provides the base address of the
destination buffer for read commands.
rd_data_en Output
This output indicates that valid read data is
available on the rd_data bus.
rd_data_offset[1:0] Output
This output provides the offset for the
destination buffer for read commands.
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