Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 352
UG586 November 30, 2016
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Chapter 2: QDR II+ Memory Interface Solution
This section defines a step-by-step debugging procedure to assist in the identification and
resolution of any issues that might arise during each phase of the design process. Details
are provided on:
• Functional verification using the UNISIM simulation models
• Design implementation verification
•Board layout verification
• Using the QDR II+ SRAM physical layer to debug board-level issues
• General board-level debug techniques
The two primary issues encountered during verification of a memory interface are:
• Calibration not completing properly
• Data corruption during normal operation
Problems might be seen in simulation, hardware, or both due to various root causes.
Figure 2-48 shows the overall flow for debugging problems associated with these two
general types of issues.
Debug Tools
Many tools are available to debug memory interface design issues. This section indicates
which resources are useful for debugging a given situation.
Example Design
QDR II+ SRAM design generation using the MIG tool produces an example design and a
user design. The example design includes a synthesizable test bench that has been fully
verified in simulation and hardware. This design can be used to observe the behavior of the
MIG tool design and can also aid in identifying board-related problems.
X-Ref Target - Figure 2-48
Figure 2-48: Virtex-7 FPGA QDR II+ SRAM MIG Tool Debug Flowchart
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#ALIBRATION&AILURE
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3IMULATION$EBUG
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