Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 95
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
- A write is requested and no write buffer pointers are available
°
A periodic read is being inserted
app_rd_data[APP_DATA_WIDTH – 1:0]
This output contains the data read from the external memory.
app_rd_data_end
This output indicates that the data on the app_rd_data[] bus in the current cycle is the
last data for the current request.
app_rd_data_valid
This output indicates that the data on the app_rd_data[] bus is valid.
app_wdf_rdy
This output indicates that the write data FIFO is ready to receive data. Write data is accepted
when both app_wdf_rdy and app_wdf_wren are asserted.
app_ref_req
When asserted, this active-High input requests that the Memory Controller send a refresh
command to the DRAM. It must be pulsed for a single cycle to make the request and then
deasserted at least until the app_ref_ack signal is asserted to acknowledge the request
and indicate that it has been sent.
app_ref_ack
When asserted, this active-High input acknowledges a refresh request and indicates that
the command has been sent from the Memory Controller to the PHY.
app_zq_req
When asserted, this active-High input requests that the Memory Controller send a ZQ
calibration command to the DRAM. It must be pulsed for a single cycle to make the request
and then deasserted at least until the app_zq_ack signal is asserted to acknowledge the
request and indicate that it has been sent.
app_zq_ack
When asserted, this active-High input acknowledges a ZQ calibration request and indicates
that the command has been sent from the Memory Controller to the PHY.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English