Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 196
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Power System and Plane Discontinuities
See 7 Series FPGAs PCB Design and Pin Planning Guide (UG483) [Ref 12].
Termination
These rules apply to termination for DDR3 SDRAM:
• Simulation (IBIS or other) is highly recommended. The loading of address (A, BA),
command (RAS_N, CAS_N, WE_N), and control (CS_N, ODT) signals depends on
various factors, such as speed requirements, termination topology, use of unbuffered
DIMMs, and multiple rank DIMMs, and can be a limiting factor in reaching a
performance target.
• Single ended 40Ω traces and termination are required for operation at 1,333 Mb/s and
higher. 50Ω is acceptable below 1,333 Mb/s. Figure 1-91 and Figure 1-92 are for 1,333
Mb/s and higher.
• Differential 80Ω traces and termination are required for operation at 1,333 Mb/s and
higher. 100Ω is acceptable below 1,333 Mb/s. Figure 1-93 is for 1,333 Mb/s and higher.
• When using a V
TT
supply, care must be taken to manage the high frequency currents
from the terminations. Bypass caps recommendation 1 µF for every four terminations
and 100 µF for every 25 terminations evenly distributed relative to the terminations. A
planelet should also be used to distribute power to the terminations.
• Address and control signals (A, BA, RAS_N, CAS_N, WE_N, CS_N, CKE, ODT)
are to be terminated with the onboard DIMM termination. If DIMM termination does
not exist or a component is being used, a 40Ω pull-up to V
TT
at the far end of the line
should be used (Figure 1-91). Except for the CK/CK_N which requires a differential
termination as shown in Figure 1-93.
•A split 80Ω termination to V
CCO
and a 80Ω termination to GND can be used
(Figure 1-92), but takes more power. For bidirectional signals, the termination is
needed at both ends of the signal. ODT should be used on the memory side. For best
performance in HP banks, DCI should be used. For best performance in HR banks,
IN_TERM (internal termination) should be used.
X-Ref Target - Figure 1-91
Figure 1-91: 40Ω Termination to V
TT
:1
½
2
4
½
6
44
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V