Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 289
UG586 November 30, 2016
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Chapter 2: QDR II+ Memory Interface Solution
Controller Options
This page shows the various controller options that can be selected.
• Frequency – This feature indicates the operating frequency for all the controllers. The
frequency block is limited by factors such as the selected FPGA and device speed grade.
• VCCAUX_IO – Set based on the period/frequency setting. 2.0V is required at the
highest frequency settings in the High Performance column. The MIG tool
automatically selects 2.0V when required. Either 1.8 or 2.0V can be used at lower
frequencies. Groups of banks share the VCCAUX_IO supply. For more information, see
the 7 Series FPGAs SelectIO™ Resources User Guide (UG471) [Ref 2].
• Memory Part – This option selects the memory part for the design. Selections can be
made from the list, or if the part is not listed, a new part can be created (Create
Custom Part). The QDR II+ SRAM devices with read latency 2.0 and 2.5 clock cycles are
supported by the design. If a desired part is not available in the list, you can generate
or create an equivalent device and then modify the output to support the desired
memory device.
• Data Width – The data width value can be selected here based on the memory part
selected. The MIG tool supports values in multiples of the individual device data widths.
X-Ref Target - Figure 2-17
Figure 2-17: Controller Options Page
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