Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 579
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
app_wdf_mask[APP_MASK_WIDTH – 1:0]
This bus indicates which bits of app_wdf_data[] are written to the external memory and
which bits remain in their current state.
app_wdf_wren
This input indicates that the data on the app_wdf_data[] bus is valid.
app_rdy
This output indicates to you whether the request currently being submitted to the UI is
accepted. If the UI does not assert this signal after app_en is asserted, the current request
must be retried. The app_rdy output is not asserted if:
°
PHY/Memory initialization is not yet completed
°
All the bank machines are occupied (can be viewed as the command buffer being
full)
- A read is requested and the read buffer is full
- A write is requested and no write buffer pointers are available
°
A periodic read is being inserted
app_rd_data[APP_DATA_WIDTH – 1:0]
This output contains the data read from the external memory.
app_rd_data_end
This output indicates that the data on the app_rd_data[] bus in the current cycle is the
last data for the current request.
app_rd_data_valid
This output indicates that the data on the app_rd_data[] bus is valid.
app_wdf_rdy
This output indicates that the write data FIFO is ready to receive data. Write data is accepted
when both app_wdf_rdy and app_wdf_wren are asserted.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English