Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 644
UG586 November 30, 2016
www.xilinx.com
Chapter 5
Multicontroller Design
Introduction
This chapter describes the specifications (including the supported features and
unsupported features) and pinout rules for multicontroller designs.
The supported and unsupported features are:
• Supports up to eight controllers
°
Multi-interface support includes the combination of all memory interfaces as DDR3
SDRAM (Native only), QDR II+ SRAM, and RLDRAM II up to total of eight
controllers. Multi-interface support with the DDR3 SDRAM AXI interface combined
with other memory interfaces is not supported.
°
Multicontroller for DDR3 SDRAM (AXI only) interface is supported up to eight
independent controllers. Multicontroller support combining DDR3 SDRAM Native
and AXI interface designs is not supported.
• Banks selected for one of the controllers are not allowed for other controllers; that is,
across the same memory interfaces and different memory interfaces.
• Memory options (frequency, data width, etc.) and all other options remain the same as
for single controller options.
• Sharing of banks across two different controllers is not allowed.
• Rules for all memory interfaces (DDR3 SDRAM, QDR II+ SRAM, and RLDRAM II) remain
the same as for single controller designs.
IMPORTANT: Memory Interface Solutions v4.1 only supports the Vivado
®
Design Suite. The ISE
®
Design Suite is not supported in this version.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English