Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 344
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
• The maximum electrical delay between any address and control signals and the
corresponding K/K# should be ±50 ps.
• There is no relation between CQ and the K clocks. K should be matched with D, and CQ
should be matched with Q (read data).
Pinout Requirements
Xilinx 7 series FPGAs are designed for very high-performance memory interfaces, and
certain rules must be followed to use the QDR II+ physical layer. Xilinx 7 series FPGAs have
dedicated logic for each byte group. Four byte groups are available in each 50-pin bank.
Each 50-pin bank consists of four byte groups that contain one DQS Clock capable I/O pair
and ten associated I/Os. Two pairs of Multi-region Clock-capable I/O (MRCC) pins are
available in a bank, and are used for placing the read clocks (CQ and CQ#).
In a typical QDR II+ write bank configuration, 9 of these 10 I/Os are used for the Write data
(D) and one is used for the byte write (BW). The write clocks (K/K#) use one of the DQS pairs
inside the write bank. Within a read bank, the read data are placed on 9 of the 10 I/Os, and
the CQ/CQ# clocks placed in the MRCC_P pins available inside the read bank.
Xilinx 7 series FPGAs have dedicated clock routing for high-speed synchronization that is
routed vertically within the I/O banks. Thus, QDR II+ memory interfaces must be arranged
in the banks vertically and not horizontally. In addition, the maximum height is three banks.
After generating a core through the MIG tool, the most optimal pinout has been selected
for the design. Manual changes through the XDC are not recommended. However, if the
XDC needs to be altered, the following rules must be taken into consideration:
• The write data bus (D) of a memory interface must be placed within a single bank. It is
required to arrange the write data bus byte wise (nine bits wide) among the FPGA byte
groups. All byte write (BW) signals of the interface are required to place in the same
bank.
• K/K# clocks must be kept in the same bank as the write data bank. They should be
placed on a DQS pin pair.
• The read data bus (Q) must be arranged byte wise (nine bits wide) among the FPGA
byte groups. Xilinx recommends keeping the complete read data bus of a memory
component within a single bank.
• The read data clocks (CQ and CQ#) must be placed on the two MRCC_P or MRCC_N pins
available in the same bank as the read data or an adjacent bank to it. Xilinx
recommends keeping the read data and read clocks in the same bank.
• All address/control signals must be placed within a single bank. The address bank
should be placed adjacent to the data write (D) bank.
•The dll_off_n signal can be placed on any free I/O available in the banks used for
the memory interface.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English