Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 592
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Precharge Policy
The controller implements an aggressive precharge policy. The controller examines the
input queue of requests as each transaction completes. If no requests are in the queue for
a currently open bank/row, the controller closes it to minimize latency for requests to other
rows in the bank. Because the queue depth is equal to the number of bank machines,
greater efficiency can be obtained by increasing the number of bank machines
(nBANK_MACHS).
As this number is increased, FPGA logic timing becomes more challenging. In some
situations, the overall system efficiency can be greater with an increased number of bank
machines and a lower memory clock frequency. Simulations should be performed with the
target design command behavior to determine the optimum setting.
Note:
The overall read latency of the MIG 7 series LPDDR2 core is dependent on how the Memory
Controller is configured, but most critically on the target traffic/access pattern and the number of
commands already in the pipeline before the read command is issued. Read latency is measured from
the point where the read command is accepted by the user or native interface. Simulation should be
run to analyze read latency.
PHY
The PHY provides a physical interface to an external LPDDR2 SDRAM. The PHY generates
the signal timing and sequencing required to interface to the memory device. It contains
the clock-, address-, and control-generation logic, write and read datapaths, and state logic
for initializing the SDRAM after power-up. In addition, the PHY contains calibration logic to
perform timing training of the read and write datapaths to account for system static and
dynamic delays.
The PHY is provided as a single HDL codebase for LPDDR2 SDRAMs. The MIG tool
customizes the SDRAM type and numerous other design-specific parameters through
top-level HDL parameters and constraints contained in a XDC file.
Overall PHY Architecture
The 7 series FPGA PHY is composed of dedicated blocks and soft calibration logic. The
dedicated blocks are structured adjacent to one another with back-to-back interconnects to
minimize the clock and datapath routing necessary to build high-performance physical
layers. Dedicated clock structures within an I/O bank referred to as byte group clocks help
minimize the number of loads driven by the byte group clock drivers. Byte group clocks are
driven by phaser blocks. The phaser blocks (PHASER_IN and PHASER_OUT) are multi-stage
programmable delay line loops that can dynamically track DQS signal variation and provide
precision phase adjustment.
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