Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 550
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
<component name>/example_design/sim
Table 4-4 lists the modules in the example_design/sim directory.
<component name>/user_design
The user_design folder contains the following:
• rtl and xdc folders
• Top-level wrapper module <component_name>.v/vhd
• Top-level modules <component_name>_mig.v/vhd and
<component_name>_mig_sim.v/vhd
The top-level wrapper file <component_name>.v/vhd has an instantiation of top-level
file <component_name>_mig.v/vhd. Top-level wrapper file has no parameter
declarations and all the port declarations are of fixed width.
Top-level files <component_name>_mig.v/vhd and
<component_name>_mig_sim.v/vhd have the same module name as
<component_name>_mig. These two files are same in all respects except that the file
<component_name>_mig_sim.v/vhd has parameter values set for simulation where
calibration is in fast mode viz., SIM_BYPASS_INIT_CAL = "FAST" etc.
IMPORTANT: The top-level file <component_name>_mig.v/vhd is used for design synthesis and
implementation, whereas the top-level file <component_name>_mig_sim.v/vhd is used in
simulations.
Table 4-4: Files in example_design/sim Directory
Name Description
mobile_ddr2_model.v These are the LPDDR2 SDRAM models.
mobile_ddr2_model_parameters.vh These files contain the LPDDR2 SDRAM model parameter setting.
ies_run.sh
(1)
Linux Executable file for simulating the design using IES
simulator.
vcs_run.sh
(1)
Linux Executable file for simulating the design using VCS
simulator.
readme.txt
(1)
Contains the details and prerequisites for simulating the designs
using Mentor Graphics Questa Advanced Simulator, IES, and VCS
simulators.
sim_tb_top.v This is the simulation top file.
Notes:
1. The ies_run.sh and vcs_run.sh files are generated in the folder mig_7series_0_ex/imports when the example design
is created using Open IP Example Design for the design generated with Component Name entered in Vivado
IDE as mig_7series_0.
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