Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 46
UG586 November 30, 2016
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
• clk_ref – This is the reference frequency input for the IDELAY control. The clk_ref
input can be generated internally or connected to an external source. A single input or
a differential pair can be selected based on the System Clock selection in the FPGA
Options page (Figure 1-22). The I/O standard is selected in a similar way as sys_clk.
• sys_rst – This is the asynchronous system reset input that can be generated internally
or driven from a pin. The MIG tool selects an appropriate I/O standard for the input
such as LVCMOS18 and LVCMOS25 for HP and HR banks, respectively. The default
polarity of sys_rst pin is active-Low. The polarity of sys_rst pin varies based on the
System Reset Polarity option chosen in FPGA Options page (Figure 1-22).
• init_calib_complete – This output indicates that the memory initialization and
calibration is complete and that the interface is ready to use. The
init_calib_complete signal is normally only used internally, but can be brought
out to a pin if desired.
• tg_compare_error – This output indicates that the traffic generator in the example
design has detected a data compare error. This signal is only generated in the example
design and is not part of the user design. This signal is not typically brought out to a
pin but can be, if desired.
Click Next to display the Summary page.
Summary
This page provides the complete details about the 7 series FPGA memory core selection,
interface parameters, IP catalog options, and FPGA options of the active project
(Figure 1-27).
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