Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 380
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Using MIG in the Vivado Design Suite
This section provides the steps to generate the Memory Interface Generator (MIG) IP core
using the Vivado Design Suite and run implementation.
1. Start the Vivado Design Suite (see Figure 3-1).
2. To create a new project, click the Create New Project option shown in Figure 3-1 to
open the page as shown in Figure 3-2.
X-Ref Target - Figure 3-1
Figure 3-1: Vivado Design Suite
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