Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 555
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
°
An FPGA byte lane should not contain pins related to two different strobe sets.
°
V
REF
I/O can be used only when the internal V
REF
is chosen.
• Verified address pin rules:
°
Address signals cannot mix with data bytes.
°
It can use any number of isolated byte lanes.
°
Memory clock pins should be allocated to DQS I/O only.
°
Except memory clock pins, any other Address/Control pin should not be allocated
to DQS.
• Verified system pin rules:
°
System clock:
- These pins should be allocated to either SR/MR CC I/O pair.
- These pins must be allocated in the Memory banks column.
- If the selected system clock type is single-ended, you need to check whether the
reference voltage pins are unallocated in the bank or the internal V
REF
is used.
°
Reference clock:
- These pins should be allocated to either SR/MR CC I/O pair.
- If the selected system clock type is single-ended, you need to check whether the
reference voltage pins are unallocated in the bank or the internal V
REF
is used.
°
Status signals:
- The sys_rst signal should be allocated in the bank where the V
REF
I/O is
unallocated or the internal V
REF
is used.
- These signals should be allocated in the non-memory banks because the I/O
standard is not compatible. The I/O standard type should be LVCMOS with at
least 1.8V.
- These signals can be allocated in any of the columns (there is no hard
requirement because these signals should reside in a memory column); however,
it is better to allocate closer to the chosen memory banks.
Quick Start Example Design
Overview
After the core is successfully generated, the example design HDL can be processed through
the Xilinx implementation toolset.
Send Feedback

Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English