Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 415
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
user_design/rtl/xdc
Table 3-7 lists the files in the user_design/xdc directory.
Verify Pin Changes and Update Design
This feature verifies the input XDC for bank selections, byte selections, and pin allocation. It
also generates errors and warnings in a separate dialog box when you click Validate on the
page. This feature is useful to verify the XDC for any pinout changes made after the design
is generated from the MIG tool. You must load the MIG generated .prj file, the original
.prj file without any modifications, and the XDC that needs to be verified. In the Vivado IP
catalog, the recustomization option should be selected to reload the project. The design is
allowed to generate only when the MIG DRC is met. Ignore warnings about validating the
pinout, which is the intent. Just validating the XDC is not sufficient; it is mandatory to
proceed with design generation to get the XDC with updated clock and phaser related
constraints and RTL top-level module for various updated Map parameters.
The Update Design feature is required in the following scenarios:
• A pinout is generated using an older version of MIG and the design is to be revised to
the current version of MIG. In MIG the pinout allocation algorithms have been changed
for certain MIG designs.
• A pinout is generated independent of MIG or is modified after the design is generated.
When a design is generated from MIG, the XDC and HDL code are generated with the
correct constraints.
qdr_rld_phy_4lanes.v
This module is the parameterizable four-lane PHY in an
I/O bank.
qdr_rld_byte_lane.v
This module contains the primitive instantiations
required within an output or input byte lane.
qdr_rld_byte_group_io.v
This module contains the parameterizable I/O logic
instantiations and the I/O terminations for a single byte
lane.
rld_phy_write_cal.v
This module contains the logic for performing write
calibration.
Notes:
1. All file names are prefixed with the MIG version number. For example, for the MIG 4.1 release module name of
rld_phy_top in generated output is now mig_7series_v4_1_rld_phy_top.
Table 3-7: Files in user_design/xdc Directory
Name Description
<component name>.xdc This file is the XDC for the core of the user design.
Table 3-6: Files in user_design/rtl/phy Directory (Cont’d)
Name
(1)
Description
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