Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 378
UG586 November 30, 2016
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Chapter 2: QDR II+ Memory Interface Solution
CLOCK_DEDICATED_ROUTE Constraints
System Clock
If the SRCC/MRCC I/O pin and PLL are not allocated in the same bank, the
CLOCK_DEDICATED_ROUTE constraint must be set to BACKBONE. QDR II+ SRAM manages
these constraints for designs generated with the System Clock option selected as
Differential/Single-Ended (at FPGA Options > System Clock).
If the design is generated with the System Clock option selected as No Buffer (at FPGA
Options > System Clock), the CLOCK_DEDICATED_ROUTE constraints based on the
SRCC/MRCC I/O and PLL allocation needs to be handled manually for the IP flow. QDR II+
SRAM does not generate clock constraints in the XDC file for the No Buffer configurations.
You must take care of the clock constraints for the No Buffer configurations in the IP flow.
Reference Clock
If the SRCC/MRCC I/O pin and MMCM are not allocated in the same bank, the
CLOCK_DEDICATED_ROUTE constraint is set to FALSE. Reference clock is a 200 MHz clock
source used to drive IODELAY CTRL logic (through an additional MMCM). This clock is not
utilized, CLOCK_DEDICADE_ROUTE (as they are limited in number), hence the FALSE value is
set. QDR II+ SRAM manages these constraints for designs generated with the System Clock
option selected as Differential/Single-Ended (at FPGA Options > System Clock).
If the design is generated with the System Clock option selected as No Buffer (at FPGA
Options > System Clock), the CLOCK_DEDICATED_ROUTE constraints based on
SRCC/MRCC I/O and MMCM allocation needs to be handled manually for the IP flow.
QDR II+ SRAM does not generate clock constraints in the XDC file for the No Buffer
configurations. You must take care of the clock constraints for the No Buffer configurations
in the IP flow.
dbg_stage2_cal[34] fd3_vld
Indicates valid ISERDES read data for the byte being
calibrated (indicated by byte_cnt). Only valid for
nCK_PER_CLK == 4.
dbg_stage2_cal[35] latency_measured[1] Indicates latency has been measured for byte lane 1
dbg_stage2_cal[36] latency_measured[2] Indicates latency has been measured for byte lane 2
dbg_stage2_cal[37] latency_measured[3] Indicates latency has been measured for byte lane 3
dbg_stage2_cal[38] error_adj_latency
Indicates error when target PHY_LATENCY cannot be
achieved
dbg_stage2_cal[127:39] Reserved Reserved
Table 2-21: Read Stage 2 Debug Signal Map (Cont’d)
Bits PHY Signal Name Description
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