Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 230
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Debug Signals
The MIG 7 series tool includes a Debug Signals Control option on the FPGA Options screen.
Enabling this feature allows calibration, tap delay, and read data signals to be monitored
using the Vivado logic analyzer feature. Selecting this option port maps the debug signals
to ILA VIO cores in the design top module. For details on enabling this debug feature, see
the “Using MIG in the Vivado Design Suite, page 21. The debug port is disabled for
functional simulation and can only be enabled if the signals are actively driven by the user
design.
Note:
"Debug Signals" are not available when using IP integrator but Integrated Logic Analyzer (ILA)
insertion is still available on the synthesized DCP. For more information, see the Vivado Design Suite
User Guide: Programming and Debugging (UG908) [Ref 16].
Vivado Design Suite Debug Feature
The Vivado Design Suite debug feature inserts ILA 3.0 and VIO 3.0 directly into your design.
The debug feature also allows you to set trigger conditions to capture application and MIG
debug signals in hardware. Captured signals can be analyzed though the Vivado logic
analyzer feature. For more information about the Vivado logic see the Vivado Design Suite
User Guide: Programming and Debugging (UG908) [Ref 16].
IMPORTANT: The ILA operates on a synchronous clock and cannot be triggered during reset. Instead,
set the trigger on an ILA signal to look for a rising edge (“R”) or falling edge (“F”) with the radix value
of the signal set to "Binary." With this trigger setting, the trigger can be armed. When the reset is
applied and released, the trigger captures the desired ILA results.
The Vivado logic analyzer feature snapshot is shown in Figure 1-96. The Hardware Debug
section has a snapshot of the older analyzer version but the debugging steps and data to be
captured remain the same.
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