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Xilinx Zynq-7000

Xilinx Zynq-7000
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Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 547
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Directory Structure and File Descriptions
Output Directory Structure
The MIG tool outputs are generated with folder name <component name>.
The output directory structure of the selected Memory Controller (MC) design from the MIG
tool is shown here. In the <component name> directory, three folders are created:
docs
example_design
user_design
X-Ref Target - Figure 4-36
Figure 4-36: Recustomize IP
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