Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 635
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN
<sys_clk_p.PAD> allowing your design to continue. This constraint disables all clock
placer rules related to the specified COMP.PIN. The use of this override is highly
discouraged as it might lead to very poor timing results. It is recommended that this error
condition be corrected in the design.
Do not drive user clocks through the I/O clocking backbone from the region(s) containing
the MIG generated memory interface to CMT blocks in adjacent regions due to resource
limitations. For more information, see the 7Series FPGAs Clocking Resources User Guide
(UG472) [Ref 10].
The MIG tool sets the VCCAUX_IO constraint based on the data rate and voltage input
selected. The generated XDC has additional constraints as needed. For example:
# PadFunction: IO_L13P_T2_MRCC_34
set_property VCCAUX_IO NORMAL [get_ports {lpddr2_dq[0]}]
set_property SLEW FAST [get_ports {lpddr2_dq[0]}]
set_property IOSTANDARD HSUL_12 [get_ports {lpddr2_dq[0]}]
set_property PACKAGE_PIN AJ11 [get_ports {lpddr2_dq[0]}]
# PadFunction: IO_L13N_T2_MRCC_34
set_property VCCAUX_IO NORMAL [get_ports {lpddr2_dq[1]}]
set_property SLEW FAST [get_ports {lpddr2_dq[1]}]
set_property IOSTANDARD HSUL_12 [get_ports {lpddr2_dq[1]}]
set_property PACKAGE_PIN AK11 [get_ports {lpddr2_dq[1]}]
For more information, see the Xilinx Timing Constraints User Guide (UG612) [Ref 15].
For LPDDR2 SDRAM interfaces that have the memory system input clock
(sys_clk_p/sys_clk_n) placed on CCIO pins within one of the memory banks, MIG
assigns the DIFF_HSUL_12 I/O standard (V
CCO
= 1.2V) to the CCIO pins.
Termination
These rules apply to termination for LPDDR2 SDRAM:
• Simulation (using IBIS or other) is highly recommended. The loading of command
address and control (CS_N) signals depends on various factors, such as speed
requirements, and termination topology. Loading can be a limiting factor in reaching a
performance target.
• If termination is used, unidirectional signals should be terminated with a resistor to V
TT
at the load. A split termination to V
CCO
and GND can be used, but takes more power.
Bidirectional signals might need termination at both ends of the signal.
• If termination is used, differential signals should be terminated with a differential
termination at the load. Bidirectional signals might need termination at both ends of
the signal.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English