Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 57
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Directory Structure and File Descriptions
Output Directory Structure
The output directory structure of the selected Memory Controller (MC) design from the MIG
tool is shown here. In the <component name> directory, three folders are created:
• docs
• example_design
• user_design
X-Ref Target - Figure 1-38
Figure 1-38: Recustomize IP
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