Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 194
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
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An unused pin exists in the adjacent byte group (T0/T3) or the CK output is
contained in the adjacent byte group.
• No more than three vertical banks from a die perspective can be used for a single
interface.
• The address/control must be in the middle I/O bank of interfaces that span three I/O
banks. All address/control must be in the same I/O bank. Address/control cannot be
split between banks.
• Control (RAS_N, CAS_N, WE_N, CS_N, CKE, ODT) and address lines must be
connected to byte groups not used for the data byte groups.
• RESET_N can be connected to any available pin within the device, including the
VRN/VRP pins if DCI cascade is used, as long as timing is met and an appropriate I/O
voltage standard is used. The GUI restricts this pin to the banks used for the interface
to help with timing, but this is not a requirement.
• Devices implemented with SSI technology have SLRs. Memory interfaces cannot span
across SLRs. Ensure that this rule is followed for the part chosen and for any other
pin-compatible parts that can also be used.
Pin Swapping
• Pins can be freely swapped within each byte group (data and address/control), except
for the DQS pair which must be on a clock-capable DQS pair and the CK which must be
on a p-n pair.
• Byte groups (data and address/control) can be freely swapped with each other.
• Pins in the address/control byte groups can be freely swapped within and between
their byte groups.
• No other pin swapping is permitted.
Bank Sharing Among Controllers
No unused part of a bank used in a memory interface is permitted to be shared with
another memory interface. The dedicated logic that controls all the FIFOs and phasers in a
bank is designed to only operate with a single memory interface and cannot be shared with
other memory interfaces. With the exception of the shared address and control in the dual
controller supported in the MIG core.
System Clock, PLL and MMCM Locations, and Constraints
The PLL and MMCM are required to be in the bank that supplies the clock to the memory to
meet the specified interface performance. The system clock input is also strongly
recommended to be in this bank. The MIG tool follows these two rules whenever possible.
The exception is a 16-bit interface in a single bank where there might not be pins available
for the clock input. In this case, the clock input needs to come from an adjacent bank
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