Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 511
UG586 November 30, 2016
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Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
7. Increment the tap values on PHASER_IN until an error occurs (tg_compare_error
should be asserted) using dbg_pi_f_inc. Record how many phaser taps it took to get
an error from the starting location. This value is the tap count to reach one side of the
window for the entire byte lane.
8. Decrease the tap values on PHASER_IN using dbg_pi_f_dec back to the starting value.
9. Clear the error recorded previously by asserting vio_dbg_clear_error.
10. Decrement the PHASER_IN taps using dbg_pi_f_dec to find the other edge of the
window until another error occurs (tg_compare_error should be asserted).
11. Record those results, return the PHASER_IN taps to the starting location and clear the
error again (vio_dbg_clear_error).
This simple technique uses the error signal that is common for the entire interface, so any
marginality in another bit or byte not being tested might affect the results. For better
results, a per-bit error signal should be used. PHASER_IN taps need to be converted into a
common unit of time to properly analyze the results.
Automated Margin Check
Manually moving taps to verify functionality is useful to check issue bits or bytes, but it can
be difficult to step through an entire interface looking for issues. For this reason, the
RLDRAM II/RLDRAM 3 Memory Interface Debug port contains automated window checking
that can be used to step through the entire interface. A simple state machine is used to take
control of the debug port signals and report results of the margin found per-bit. Currently,
the automated window check only uses PHASER_IN to check window sizes, so depending on
the tap values after calibration, the left edge of the read data window might not be found
properly.
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