Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 252
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Debugging OCLKDELAYED Calibration Failures
Calibration Overview
The 7 series MMCM has outputs with "fine phase shift" capability. This fine phase shift
capability is relatively linear and with fairly high resolution. The algorithm finds at least two
edges that are either the edges of the data valid window or the edges of the noise region
using Phaser_Out stage 3 taps. The MMCM fine phase shift is used to align the MMCM clock
to these detected edges to determine the center of the data valid window using MMCM
taps. Finally, the write DQS is edge-aligned with the already centered MMCM clock using
Phaser_Out stage 3 taps.
There are three substages in this step:
1. Set Phaser_Out stage 3 limit for OCLKDELAY calibration using MMCM per byte. This
stage determines the limits of stage 3 tap movement during the edge detection
substage.
2. Detect edges of the write DQ window using simple pattern. These modules perform edge
detection by scanning the write DQ window using stage 3 within the limits determined
by the limit module.
3. Set DQS to the center of write DQ window using MMCM phaser shift. Centering stage
during which the write DQS is centered in the write DQ window based on the edges
found during the edge detection stage.
Debug
This stage of calibration can fail if no edges are detected (highly unlikely). Sub-optimal
OCLKDELAYED calibration can result in data bit errors during normal operation. This occurs
because the DQS to DQ 90° relationship is not correct. Full analysis of this calibration stage
is critical.
•Probe the DQS to DQ phase relationship at the memory. DQS should be center aligned
to DQ.
•Using dbg_oclkdelay_calib_done = R as the ILA trigger, capture the below signals
and record the results in the “7 Series DDR3 Calibration Results” spreadsheet.
• Look at how many edges (up to three) were found. Less than three edges can be found
when running around 400 MHz or at higher frequencies when the write level tap values
are around 56 taps.
Table 1-78: Debug Signals of Interest for OCLKDELAYED Calibration
Signal Name Description
dbg_oclkdelay_calib_start Signifies the start of the OCLKDELAY stage of calibration.
dbg_oclkdelay_calib_done Signifies the end of the OCLKDELAY stage of calibration.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English