Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 417
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
°
Reference clock:
- These pins should be allocated to either SR/MR CC I/O pair.
- If the selected system clock type is single-ended, you need to check whether the
reference voltage pins are unallocated in the bank or the internal V
REF
is used.
°
Status signals:
-The sys_rst signal should be allocated in the bank where the V
REF
I/O is
unallocated or the internal V
REF
is used.
- These signals should be allocated in the non-memory banks because the I/O
standard is not compatible. The I/O standard type should be LVCMOS with at
least 1.8V.
- These signals can be allocated in any of the columns (there is no hard
requirement because these signals should reside in a memory column); however,
it is better to allocate closer to the chosen memory banks.
Quick Start Example Design
Overview
After the core is successfully generated, the example design HDL can be processed through
the Xilinx implementation toolset.
Implementing the Example Design
For more information on using an IP example design, see the Vivado Design Suite User
Guide: Designing with IP (UG896) [Ref 7].
Simulating the Example Design (for Designs with the Standard User Interface)
The MIG tool provides a synthesizable test bench to generate various traffic data patterns
to the Memory Controller (MC). This test bench consists of a rld_memc_ui_top wrapper,
a traffic_generator that generates traffic patterns through the user interface to a
rld_ui_top core, and an infrastructure core that provides clock resources to the
rld_memc_ui_top core. A block diagram of the example design test bench is shown in
Figure 3-35.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English