Xilinx Zynq-7000 - Page 418

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 418
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
X-Ref Target - Figure 3-35
Figure 3-35: Synthesizable Example Design Block Diagram
rld_memc_ui_top
rld_phy_top
rld_mc
RLDRAM II/
RLDRAM 3
rld_ui_top
Example Design
traffic_gen_top
error
Parameter:
BEGIN_ADDR
END_ADDR
nCK_PER_CLK
user_design_top Wrapper
iodelayctrl infrastructure
user_design_top
user_rd_data
user_rd_valid
user_cmd_en
user_cmd
user_addr
user_ba
user_wr_en
user_wr_data
user_wr_dm
user_afifo_empty
user_afifo_aempty
user_afifo_full
user_afifo_afull
user_wdfifo_empty
user_wdfifo_aempty
user_wdfifo_full
user_wdfifo_afull
cmd_en
cmd_valid
cmd_in
addr_in
ba_in
cmd_empty
data_empty
sim_tb_top
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