Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 110
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
UE_FFD[31:0]
This register stores the (uncorrected) failing data (Bits[31:0]) of the first occurrence of an
access with an uncorrectable error. When the UE_STATUS bit in the ECC Status register is
cleared, this register is re-enabled to store the data of the next uncorrectable error. Storing
of the failing data is enabled after reset.
UE_FFD[63:32]
This register stores the (uncorrected) failing data (Bits[63:32]) of the first occurrence of an
access with an uncorrectable error. When the UE_STATUS bit in the ECC Status register is
cleared, this register is re-enabled to store the data of the next uncorrectable error. Storing
of the failing data is enabled after reset.
UE_FFD[95:64]
Note: This register is only used when the DQ_WIDTH == 144.
This register stores the (uncorrected) failing data (Bits[95:64]) of the first occurrence of an
access with an uncorrectable error. When the UE_STATUS bit in the ECC Status register is
cleared, this register is re-enabled to store the data of the next uncorrectable error. Storing
of the failing data is enabled after reset.
Table 1-38: Uncorrectable Error First Failing Data [31:0] Register Bit Definitions
Bits Name Core Access Reset Value Description
31:0 UE_FFD[31:0] R 0
Data (Bits[31:0]) of the first occurrence of an
uncorrectable error.
Table 1-39: Uncorrectable Error First Failing Data [63:32] Register Bit Definitions
Bits Name Core Access Reset Value Description
31:0 UE_FFD [63:32] R 0
Data (Bits[63:32]) of the first occurrence of an
uncorrectable error.
Table 1-40: Uncorrectable Error First Failing Data [95:64] Register Bit Definitions
Bits Name Core Access Reset Value Description
31:0 UE_FFD[95:64] R 0
Data (Bits[95:64]) of the first occurrence of an
uncorrectable error.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English