Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 108
UG586 November 30, 2016
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
this register is re-enabled to store the data of the next correctable error. Storing of the
failing data is enabled after reset.
CE_FFD[95:64]
Note: This register is only used when DQ_WIDTH == 144.
This register stores the (corrected) failing data (Bits[95:64]) of the first occurrence of an
access with a correctable error. When the CE_STATUS bit in the ECC Status register is cleared,
this register is re-enabled to store the data of the next correctable error. Storing of the
failing data is enabled after reset.
CE_FFD[127:96]
Note: This register is only used when DQ_WIDTH == 144.
This register stores the (corrected) failing data (Bits[127:96]) of the first occurrence of an
access with a correctable error. When the CE_STATUS bit in the ECC Status register is cleared,
this register is re-enabled to store the data of the next correctable error. Storing of the
failing data is enabled after reset.
CE_FFE
This register stores the ECC bits of the first occurrence of an access with a correctable error.
When the CE_STATUS bit in the ECC Status register is cleared, this register is re-enabled to
store the ECC of the next correctable error. Storing of the failing ECC is enabled after reset.
Table 1-31: Correctable Error First Failing Data [63:32] Register Bit Definitions
Bits Name Core Access Reset Value Description
31:0 CE_FFD[63:32] R 0
Data (Bits[63:32]) of the first occurrence of a
correctable error.
Table 1-32: Correctable Error First Failing Data [95:64] Register Bit Definitions
Bits Name Core Access Reset Value Description
31:0 CE_FFD[95:64] R 0
Data (Bits[95:64]) of the first occurrence of a
correctable error.
Table 1-33: Correctable Error First Failing Data [127:96] Register Bit Definitions
Bits Name Core Access Reset Value Description
31:0 CE_FFD [127:96] R 0
Data (Bits[127:96]) of the first occurrence of a
correctable error.
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