Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 571
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
4. In the Flow Navigator window, select Run Simulation and select Run Behavioral
Simulation as shown in Figure 4-40.
5. Vivado invokes Questa Advanced Simulator and simulations are run in the Questa
Advanced Simulator tool. For more information, see the Vivado Design Suite User Guide:
Logic Simulation (UG900) [Ref 8].
Simulation Flow Using VCS
1. In the Open IP Example Design Vivado project, under Flow Navigator select
Simulation Settings.
2. Select Target simulator as Verilog Compiler Simulator (VCS).
X-Ref Target - Figure 4-41
Figure 4-41: Simulation with Questa Advanced Simulator
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V