Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 424
UG586 November 30, 2016
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Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
5: DGEN_WALKING1. Walking 1s are on the DQ pins. The starting position of 1 depends
on the address value.
6: DGEN_WALKING0. Walking 0s are on the DQ pins. The starting position of 0 depends
on the address value.
7: DGEN_PRBS. A 32-stage LFSR generates random data and is seeded by the starting
address. The PRBS data pattern only works together with a PRBS address or a sequential
address.
Core Architecture
Overview
Figure 3-37 shows a high-level block diagram of the RLDRAM II and RLDRAM 3 memory
interface solution. This figure shows both the internal FPGA connections to the client
interface for initiating read and write commands, and the external interface to the memory
device.
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