Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 425
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
X-Ref Target - Figure 3-37
Figure 3-37: High-Level Block Diagram of RLDRAM II/RLDRAM 3 Interface Solution
CLK
SYS?RST
RST?CLK
RST
MEM?REFCLK
FREQ?REFCLK
CLK?REF
PLL?LOCK
SYNC?PULSE
USER?CMD?EN
USER?CMD
USER?ADDR
USER?BA
USER?WR?EN
USER?WR?DATA
USER?WR?DM
USER?AFIFO?EMPTY
USER?AFIFO?FULL
USER?AFIFO?AEMPTY
USER?AFIFO?AFULL
USER?WDFIFO?EMPTY
USER?WDFIFO?FULL
USER?WDFIFO?AEMPTY
USER?WDFIFO?AFULL
USER?RD?VALID
USER?RD?DATA
INIT?CALIB?COMPLETE
RLD?CK?P
RLD?CK?N
RLD?CS?N
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RLD?DK?P
RLD?DK?N
RLD?WE?N
RLD?REF?N
RLD?A
RLD?BA
RLD?DQ
RLD?DM
RLD?QK?P
RLD?QK?N
RLD?QVLD
RLD?RESET?N
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