Xilinx Zynq-7000 - Expected Vivado Logic Analyzer Tool Results

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 257
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Expected Vivado Logic Analyzer Tool Results
X-Ref Target - Figure 1-103
Figure 1-103: Trigger = dbg_wrcal_done
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