Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 498
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Any timing violations that are encountered must be isolated. The timing report output by
TRACE (.twx/.twr) should be analyzed to determine if the failing paths exist in the MIG
tool RLDRAM II design or the UI (backend application) to the MIG tool design. If failures are
encountered, you must ensure the build options (that is, XST, MAP, PAR) specified in the file
are used.
If failures still exist, Xilinx has many resources available to aid in closing timing. The
PlanAhead™ tool [Ref 19] improves performance and quality of the entire design. The Xilinx
Timing Constraints User Guide (UG612) [Ref 15] provides valuable information on all
available Xilinx constraints.
Hardware Debug
Figure 3-78 shows the debug flow for hardware.
Clocking
The external clock source should be measured to ensure frequency, stability (jitter), and
usage of the expected FPGA pin. You must ensure that the design follows all clocking
guidelines. If clocking guidelines have been followed, the interface should be run at a
slower speed. Not all designs or boards can accommodate slower speeds. Lowering the
frequency increases the marginal setup or hold time, or both, due to PCB trace mismatch,
poor signal integrity, or excessive loading. When lowering the frequency, the MIG tool
should be rerun to regenerate the design with the lower clock frequency. Portions of the
calibration logic are sensitive to the CLK_PERIOD parameter; thus, manual modification of
the parameter is discouraged.
X-Ref Target - Figure 3-78
Figure 3-78: Hardware Debug Flowchart
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