Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 206
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
System Clock, PLL Location, and Constraints
The PLL is required to be in the bank that supplies the clock to the memory to meet the
specified interface performance. The system clock input is also strongly recommended to
be in this bank. The MIG tool follows these two rules whenever possible. The exception is a
16-bit interface in a single bank where there might not be pins available for the clock input.
In this case, the clock input needs to come from an adjacent bank through the frequency
backbone to the PLL. The system clock input to the PLL must come from clock capable I/O.
The system clock input can only be used for an interface in the same column. The system
clock input cannot be driven from another column. The additional PLL or MMCM and clock
routing required for this induces too much additional jitter.
Unused outputs from the PLL can be used as clock outputs. Only the settings for these
outputs can be changed. Settings related to the overall PLL behavior and the used outputs
must not be disturbed.
A PLL cannot be shared among interfaces.
See Clocking Architecture, page 119 for information on allowed PLL parameters.
Configuration
The XDC contains timing, pin, and I/O standard information. The sys_clk constraint sets
the operating frequency of the interface and is set through the MIG GUI. The MIG GUI must
be rerun if this needs to be altered, because other internal parameters are affected. For
example:
create_clock -period 1.875 [get_ports sys_clk_p]
The clk_ref constraint sets the frequency for the IDELAY reference clock, which is
typically 200 MHz. For example:
create_clock -period 5 [get_ports clk_ref_p]
The I/O standards are set appropriately for the DDR2 interface with LVCMOS18, SSTL18_II,
SSTL18_II_T_DCI, DIFF_SSTL18_II, or DIFF_SSTL18_II_T_DCI, as appropriate. LVDS_25 is used
for the system clock (sys_clk) and I/O delay reference clock (clk_ref). These standards
can be changed, as required, for the system configuration. These signals are brought out to
the top-level for system connection:
• sys_rst – This is the main system reset (asynchronous). The reset signal must be applied
for a minimum pulse width of 5 ns.
• init_calib_complete – This signal indicates when the internal calibration is done and
that the interface is ready for use.
• tg_compare_error – This signal is generated by the example design traffic generator, if
read data does not match the write data.
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English