Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 614
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Command Path
When the user logic app_en signal is asserted and the app_rdy signal is asserted from the
UI, a command is accepted and written to the FIFO by the UI. The command is ignored by
the UI whenever app_rdy is deasserted. The user logic needs to hold app_en High along
with the valid command and address values until app_rdy is asserted as shown in
Figure 4-58.
A non back-to-back write command can be issued as shown in Figure 4-59. This figure
depicts three scenarios for the app_wdf_data, app_wdf_wren, and app_wdf_end
signals, as follows:
1. Write data is presented along with the corresponding write command (second half of
BL8).
2. Write data is presented before the corresponding write command.
3. Write data is presented after the corresponding write command, but should not exceed
the limitation of two clock cycles.
For write data that is output after the write command has been registered, as shown in
Note 3, the maximum delay is two clock cycles.
Remapped Address with TG_TEST
ROW Address Bits
BANK
Address
Bits
COLUMN Address Bits
2726 252423222120191817161514131211109876543210
R0 C9 C8 R4 R3 B2 B1 B0 R14R13R12R11R10R9R8C7C6C5R2R1R7R6R5C4C3C2C1C0
Original Mapping of the Address Bits
X-Ref Target - Figure 4-58
Figure 4-58: UI Command Timing Diagram with app_rdy Asserted
5'?C??
CLK
APP?CMD
72)4%
APP?ADDR
!DDR
APP?EN
APP?RDY
#OMMANDISACCEPTEDWHENAPP?RDYIS(IGHANDAPP?ENIS(IGH
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