Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 615
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
X-Ref Target - Figure 4-59
Figure 4-59: UI Interface Write Timing Diagram (Memory Burst Type = BL8)
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