Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 634
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Configuration
The XDC contains timing, pin, and I/O standard information. The sys_clk constraint sets
the operating frequency of the interface and is set through the MIG GUI. The MIG GUI must
be rerun if this needs to be altered, because other internal parameters are affected. For
example:
create_clock -period 1.875 [get_ports sys_clk_p]
The clk_ref constraint sets the frequency for the IDELAY reference clock, which is
typically 200 MHz. For example:
create_clock -period 5 [get_ports clk_ref_p]
The I/O standards are set appropriately for the LPDDR2 interface with HSUL_12, as
appropriate. If system clock (sys_clk*) and I/O delay reference clock (clk_ref*) are
allocated in LPDDR2 memory interface allocated bank, then the I/O Standards would need
to be DIFF_HSLU_12 or HSUL_12 depending on whether these clocks are differential or
single-ended. If these clocks are placed outside the LPDDR2 interface banks, then the I/O
Standards are LVDS_25 or LVCMOS25 (depending on whether these clocks are differential or
single-ended). These standards can be changed, as required, for the system configuration.
These signals are brought out to the top-level for system connection:
• sys_rst – This is the main system reset (asynchronous).
• init_calib_complete – This signal indicates when the internal calibration is done and
that the interface is ready for use.
• tg_compare_error – This signal is generated by the example design traffic generator, if
read data does not match the write data.
These signals are all set to LVCMOS25 and can be altered as needed for the system design.
They can be generated and used internally instead of being brought out to pins.
A 16-bit wide interface might need to have the system clock in a bank above or below the
bank with the address/control and data. In this case, the MIG tool puts an additional
constraint in the XDC. An example is shown here:
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sys_clk_p]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hierarchical *pll*CLKIN1]
This results in a warning listed during PAR. This warning can be ignored.
WARNING:Place:1402 - A clock IOB/PLL clock component pair have been found that are
not placed at an optimal clock IOB/PLL site pair. The clock IOB component <sys_clk_p> is
placed at site <IOB_X1Y76>. The corresponding PLL component
<u_backb16/u_ddr2_infrastructure/plle2_i> is placed at site <PLLE2_ADV_X1Y2>. The
clock I/O can use the fast path between the IOB and the PLL if the IOB is placed on a Clock
Capable IOB site that has dedicated fast path to PLL sites within the same clock region.
You might want to analyze why this issue exists and correct it. This is normally an ERROR
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English