Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 37
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
AXI Parameter Options
This feature allows the selection of AXI parameters for the controller (Figure 1-20). These
are standard AXI parameters or parameters specific to the AXI4 interface. Details are
available in the ARM
®
AMBA
®
specifications [Ref 4].
These parameters specific to the AXI4 interface logic can be configured:
• Address Width and AXI ID Width – When invoked from XPS, address width and ID
width settings are automatically set by XPS so the options are not shown.
• Base and High Address – Sets the system address space allocated to the Memory
Controller. These values must be a power of 2 with a size of at least 4 KB, and the base
address must be aligned to the size of the memory space.
• Narrow Burst Support – Deselecting this option allows the AXI4 interface to remove
logic to handle AXI narrow bursts to save resources and improving timing. XPS
normally auto-calculates whether narrow burst support can be disabled based on the
known behavior of connected AXI masters.
• Arbitration Scheme – Selects the arbitration scheme between read and write address
channels.
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