Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 36
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
The Create Custom Part page includes all the specifications of the memory component
selected in the Select Base Part pull-down menu.
3. Enter the appropriate memory part name in the text box.
4. Select the suitable base part from the Select Base Part list.
5. Edit the value column as needed.
6. Select the suitable values from the Row, Column, and Bank options as per the
requirements.
7. After editing the required fields, click Save. The new part is saved with the selected
name. This new part is added in the Memory Parts list on the Controller Options page.
It is also saved into the database for reuse and to produce the design.
8. Click Next to display the Memory Options page (or the AXI Parameter Options page
if AXI Enable is checked on the Memory Type selection page).
X-Ref Target - Figure 1-19
Figure 1-19: Create Custom Part
UG586_c1_21_110610
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V