Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 33
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Controller Options
This page shows the various controller options that can be selected (Figure 1-17).
TIP: The use of the Memory Controller is optional. The Physical Layer, or PHY, can be used without the
Memory Controller. The Memory Controller RTL is always generated by the MIG tool, but this output
need not be used. See Physical Layer Interface (Non-Memory Controller Design), page 174 for more
information. Controller-only settings such as ORDERING are not needed in this case, and the defaults
can be used. Settings pertaining to the PHY, such as the Clock Period, are used to set the PHY
parameters appropriately.
If the design has multiple controllers, the controller options page is repeated for each of the
controllers. This page is partitioned into a maximum of nine sections. The number of
partitions depends on the type of memory selected. The controller options page also
contains these pull-down menus to modify different features of the design:
X-Ref Target - Figure 1-17
Figure 1-17: Controller Options Page
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