Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 294
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
Extended FPGA Options
Figure 2-22 shows the Extended FPGA Options page.
• Digitally Controlled Impedance (DCI) – When selected, this option internally
terminates the signals from the QDR II+ SRAM read path. DCI is available in the High
Performance Banks.
• Internal Termination for High Range Banks – The internal termination option can be
set to 40, 50, or 60Ω or disabled. This termination is for the read datapath from the
QDR II+ SRAM. This selection is only for High Range banks.
X-Ref Target - Figure 2-22
Figure 2-22: Extended FPGA Options Page
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V