Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 528
UG586 November 30, 2016
www.xilinx.com
Chapter 4: LPDDR2 SDRAM Memory Interface Solution
Creating 7 Series FPGA LPDDR2 SDRAM Memory Controller Block Design
Memory Selection
This page displays all memory types that are supported by the selected FPGA family.
1. Select the LPDDR2 SDRAM controller type.
2. Click Next to display the Controller Options page (Figure 4-16).
Controller Options
This page shows the various controller options that can be selected (Figure 4-17).
TIP: The use of the Memory Controller is optional. The Physical Layer, or PHY, can be used without the
Memory Controller. The Memory Controller RTL is always generated by the MIG tool, but this output
need not be used. Controller only settings such as ORDERING are not needed in this case, and the
defaults can be used. Settings pertaining to the PHY, such as the Clock Period, are used to set the PHY
parameters appropriately.
X-Ref Target - Figure 4-16
Figure 4-16: Memory Type and Controller Selection
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V