Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 359
UG586 November 30, 2016
www.xilinx.com
Chapter 2: QDR II+ Memory Interface Solution
5. Vivado invokes VCS and simulations are run in the VCS tool. For more information, see
the Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 8].
Simulation Flow Using IES
1. In the Open IP Example Design Vivado project, under Flow Navigator select
Simulation Settings.
2. Select Target simulator as Incisive Enterprise Simulator (IES).
a. Browse to the Compiled libraries location and set the path on Compiles libraries
location option.
b. Under the Compilation tab, set the ies.compile.ncvlog.more_options to
-sv.
c. Under the Elaboration tab, set the ies.elaborate.ncelab.more_options to
-namemap_mixgen.
d. Under the Simulation tab, set the ies.simulate.runtime to 1 ms (there are
simulation RTL directives which stop the simulation after certain period of time
which is less than 1 ms) as shown in Figure 2-54.
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V