Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 229
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Answer Records for this core can also be located by using the Search Support box on the
main Xilinx support web page
. To maximize your search results, use proper keywords such
as:
• Product name
• Tool message(s)
• Summary of the issue encountered
A filter search is available after results are returned to further target the results.
Answer Record for the DDR2/DDR3 Cores Generated by MIG IP core
AR: 54025
for Vivado
Technical Support
Xilinx provides technical support at Xilinx support web page for this product when used as
described in the product documentation. Xilinx cannot guarantee timing, functionality, or
support if you do any of the following:
• Implement the solution in devices that are not defined in the documentation.
• Customize the solution beyond that allowed in the product documentation.
• Change any section of the design labeled DO NOT MODIFY.
To contact Xilinx Technical Support, navigate to the Xilinx Support web page
.
Note:
Access to WebCase is not available in all cases. Log in to the WebCase tool to see your specific
support options.
Debug Tools
There are many tools available to address MIG IP core design issues. It is important to know
which tools are useful for debugging various situations.
Example Design
Generation of a DDR2 or DDR3 design through the MIG 7 series tool produces an example
design and a user design. The example design includes a synthesizable test bench with a
traffic generator that is fully verified in simulation and hardware. This example design can
be used to observe the behavior of the MIG 7 series design and can also aid in identifying
board-related issues. For complete details on the example design, see the Quick Start
Example Design, page 65. This section describes using the example design to perform
hardware validation.
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